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general description the max19586 is a 3.3v, high-speed, high-perfor- mance analog-to-digital converter (adc) featuring a fully differential wideband track-and-hold (t/h) and a 16-bit converter core. the max19586 is optimized for multichannel, multimode receivers, which require the adc to meet very stringent dynamic performance requirements. with a -82dbfs noise floor, the max19586 allows for the design of receivers with supe- rior sensitivity requirements. at 80msps, the max19586 achieves a 79.2db signal-to- noise ratio (snr) and an 84.3dbc/100dbc single-tone spurious-free dynamic range (sfdr) performance (sfdr1/sfdr2) at f in = 70mhz. the max19586 is not only optimized for excellent dynamic performance in the 2nd nyquist region, but also for high-if input fre- quencies. for instance, at 130mhz, the max19586 achieves an 82.5dbc sfdr and its snr performance stays flat (within 2.5db) throughout the 4th nyquist region. this level of performance makes the part ideal for high-performance digital receivers. the max19586 operates from a 3.3v analog supply voltage and a 1.8v digital voltage, features a 2.56v p-p full-scale input range, and allows for a guaranteed sam- pling speed of up to 80msps. the input track-and-hold stage operates with a 600mhz full-scale, full-power bandwidth. the max19586 features parallel, low-voltage cmos- compatible outputs in two?-complement output format. the max19586 is manufactured in an 8mm x 8mm, 56-pin thin qfn package with exposed paddle (ep) for low thermal resistance, and is specified for the extend- ed industrial (-40? to +85?) temperature range. applications cellular base-station transceiver systems (bts) wireless local loop (wll) multicarrier receivers multistandard receivers e911 location receivers high-performance instrumentation antenna array processing features 80msps minimum sampling rate -82dbfs noise floor excellent dynamic performance 80db/79.2db snr at f in = 10mhz/70mhz and -2dbfs 96dbc/102dbc single-tone sfdr1/ sfdr2 at f in = 10mhz 84.3dbc/100dbc single-tone sfdr1/ sfdr2 at f in = 70mhz less than 0.1ps sampling jitter 1.1w power dissipation 2.56v p-p fully differential analog input voltage range cmos-compatible two?-complement data output separate data valid clock and over-range outputs flexible input clock buffer 3.3v analog power supply; 1.8v digital output supply small 8mm x 8mm x 0.8mm 56-pin thin qfn package ev kit available for max19586 (order max19586evkit) max19586 high-dynamic-range, 16-bit, 80msps adc with -82dbfs noise floor ________________________________________________________________ maxim integrated products 1 top view max19586 thin qfn 8mm x 8mm 15 17 16 18 19 20 21 22 23 24 25 26 27 28 n.c. n.c. av dd av dd av dd agnd agnd agnd av dd av dd av dd refout refin agnd av dd av dd n.c. dor dgnd dv dd dav d15 d14 d13 d12 d11 d10 d9 48 47 46 45 44 43 54 53 56 55 52 51 50 49 1 2 3 4 5 6 7 8 9 1011121314 42 41 40 39 38 37 36 35 34 33 32 31 30 29 agnd agnd agnd inn inp agnd agnd agnd agnd clkn clkp agnd av dd av dd dgnd dgnd dv dd d0 d1 d2 d3 d4 d5 d6 d7 d8 dv dd dv dd pin configuration ordering information 19-3758; rev 0; 8/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available + denotes lead-free package. part temp range pin-package pkg code max19586etn -40 c to +85 c 56 thin qfn-ep t5688-2 max19586etn+ -40 c to +85 c 56 thin qfn-ep t5688-2
max19586 high-dynamic-range, 16-bit, 80msps adc with -82dbfs noise floor 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (av dd = 3.3v, dv dd = 1.8v, agnd = dgnd = 0, inp and inn driven differentially, internal reference clkp and clkn driven differentially, c l = 5pf at digital outputs, f clk = 80mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c, unless otherwise noted.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd to agnd ..................................................... -0.3v to +3.6v dv dd to dgnd..................................................... -0.3v to +2.4v agnd to dgnd.................................................... -0.3v to +0.3v inp, inn, clkp, clkn, refp, refn, refin, refout to agnd....................-0.3v to (av dd + 0.3v) d0 d15, dav, dor, dav to gnd...........-0.3v to (dv dd + 0.3v) continuous power dissipation (t a = +70 c) 56-pin thin qfn (derate 47.6mw/ c above +70 c) .........................3809.5mw operating temperature range ..........................-40 c to +85 c thermal resistance ja ..................................................21 c/w thermal resistance jc .................................................0.6 c/w junction temperature ......................................................+150 c storage temperature range .............................-60 c to +150 c lead temperature (soldering, 10s) .................................+300 c parameter symbol conditions min typ max units dc accuracy resolution n 16 bits offset error vos 0 10 20 mv gain error ge -3.5 +3.5 %fs analog inputs (inp, inn) input voltage range v diff fully differential input, v in = v inp - v inn 2.56 v p-p common-mode voltage v cm internally self-biased 2.2 v differential input resistance r in 10 20% k ? differential input capacitance c in 7pf full-power analog bandwidth bw -3db -3db rolloff for fs input 600 mhz reference input/output (refin, refout) reference input voltage range refin 1.28 10% v reference output voltage refout 1.28 v dynamic specifications (f clk = 80msps) thermal plus quantization noise floor nf a in < -35dbfs -82 dbfs f in = 10mhz, a in = -2dbfs 80 f in = 70mhz, a in = -2dbfs 77.5 79.2 f in = 100mhz, a in = -2dbfs 78.5 f in = 130mhz, a in = -2dbfs 77.9 signal-to-noise ratio (first 4 harmonics excluded) (notes 2, 3) snr f in = 168mhz, a in = -2dbfs 77.2 db f in = 10mhz, a in = -2dbfs 79.6 f in = 70mhz, a in = -2dbfs 75 77.6 f in = 100mhz, a in = -2dbfs 77.4 f in = 130mhz, a in = -2dbfs 76.4 signal-to-noise plus distortion (notes 2, 3) sinad f in = 168mhz, a in = -2dbfs 72.7 db
max19586 high-dynamic-range, 16-bit, 80msps adc with -82dbfs noise floor _______________________________________________________________________________________ 3 electrical characteristics (continued) (av dd = 3.3v, dv dd = 1.8v, agnd = dgnd = 0, inp and inn driven differentially, internal reference clkp and clkn driven differentially, c l = 5pf at digital outputs, f clk = 80mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units f in = 10mhz, a in = -2dbfs 96 f in = 70mhz, a in = -2dbfs 80 84.3 f in = 100mhz, a in = -2dbfs 84 f in = 130mhz, a in = -2dbfs 82.5 spurious-free dynamic range (worst harmonic, 2nd and 3rd) sfdr1 f in = 168mhz, a in = -2dbfs 78 dbc f in = 10mhz, a in = -2dbfs 102 f in = 70mhz, a in = -2dbfs 90 100 f in = 100mhz, a in = -2dbfs 92 f in = 130mhz, a in = -2dbfs 94 spurious-free dynamic range (worst harmonic, 4th and higher) (note 3) sfdr2 f in = 168mhz, a in = -2dbfs 90 dbc f in = 10mhz, a in = -2dbfs -100 f in = 70mhz, a in = -2dbfs -95 -84 f in = 100mhz, a in = -2dbfs -94 f in = 130mhz, a in = -2dbfs -88.8 second-order harmonic distortion hd2 f in = 168mhz, a in = -2dbfs -78 dbc f in = 10mhz, a in = -2dbfs -96 f in = 70mhz, a in = -2dbfs -84.3 -80 f in = 100mhz, a in = -2dbfs -84 f in = 130mhz, a in = -2dbfs -82.5 third-order harmonic distortion hd3 f in = 168mhz, a in = -2dbfs -78 dbc two-tone intermodulation distortion ttimd f in1 = 65.1mhz, a in = -8dbfs f in2 = 70.1mhz, a in = -8dbfs -85.2 dbc two-tone sfdr ttsfdr f in1 = 65.1mhz, f in2 = 70.1mhz -100dbfs < a in < -10dbfs 99 dbfs conversion rate maximum conversion rate f clkmax 80 mhz minimum conversion rate f clkmin 20 mhz aperture jitter t j 0.094 ps rms clock inputs (clkp, clkn) differential input swing v diffclk fully differential inputs 1.0 to 5.0 v p-p common-mode voltage v cmclk self-biased 1.6 v differential input resistance r inclk 10 k ? differential input capacitance c inclk 3pf cmos-compatible digital outputs (d0 d15, dor, dav) digital output high voltage v oh i source = 200a dv dd - 0.2 v digital output low voltage v ol i sink = 200a 0.2 v
max19586 high-dynamic-range, 16-bit, 80msps adc with -82dbfs noise floor 4 _______________________________________________________________________________________ electrical characteristics (continued) (av dd = 3.3v, dv dd = 1.8v, agnd = dgnd = 0, inp and inn driven differentially, internal reference clkp and clkn driven differentially, c l = 5pf at digital outputs, f clk = 80mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units timing specification (figures 4, 5), c l = 5pf (d0 d15, dor); c l = 15pf (dav) clkp - clkn high t clkp (note 2) 5 ns clkp - clkn low t clkn (note 2) 5 ns effective aperture delay t ad -300 ps output data delay t dat 3.3 ns data valid delay t dav (note 2) 2.8 3.8 5.0 ns pipeline latency t p 7 clock cycles clkp rising edge to data not valid t dnv (note 2) 1.2 ns clkp rising edge to data guaranteed valid t dgv (note 2) 6.5 ns data setup time before rising dav t s clock duty cycle = 50% (note 2) 3 ns data hold time after rising dav t h clock duty cycle = 50% (note 2) 3 ns power supplies analog power-supply voltage av dd 3.13 3.3 3.46 v digital output power-supply voltage dv dd 1.7 1.8 1.9 v analog power-supply current i avdd 320 382 ma digital output power-supply current i dvdd 28 35 ma power dissipation p diss 1105 1325 mw note 1: +25 c guaranteed by production test, < +25 c guaranteed by design and characterization. typical values are at t a = +25 c. note 2: parameter guaranteed by design and characterization. note 3: ac parameter measured in a 32,768-point fft record, where the first 2 bins of the fft and 2 bins on either side of the carrier are excluded.
max19586 high-dynamic-range, 16-bit, 80msps adc with -82dbfs noise floor _______________________________________________________________________________________ 5 -120 -100 -80 -60 -40 -20 0 010 5 152025303540 fft plot (32,768-point record) max19586 toc01 analog input frequency (mhz) amplitude (dbfs) f clk = 80.00012288mhz f in = 10.10011317mhz a in = -2.02dbfs snr = 80db sinad = 79.8db sfdr1 = 96.2dbc sfdr2 = 101dbc hd2 = -99.6dbc hd3 = -96.2dbc 2 3 -120 -100 -80 -60 -40 -20 0 010 5 152025303540 fft plot (32,768-point record) max19586 toc02 analog input frequency (mhz) amplitude (dbfs) 2 3 f clk = 80.00012288mhz f in = 70.16368199mhz a in = -2.06dbfs snr = 79.3db sinad = 77.7db sfdr1 = 83.3dbc sfdr2 = 98.2dbc hd2 = -93.5dbc hd3 = -83.3dbc -140 -100 -120 -80 -60 -40 -20 0 010 5 152025303540 fft plot (261,244-point data record) max19586 toc03 analog input frequency (mhz) amplitude (dbfs) 3 2 f clk = 80.00012288mhz f in = 130.00050486mhz a in = -1.82dbfs snr = 77.7db sinad = 76.4db sfdr1 = 83.1dbc sfdr2 = 91.2dbc hd2 = -89.4dbc hd3 = -83.1dbc 70 72 76 80 74 78 82 0 406080 20 100 120 140 160 180 snr/sinad vs. analog input frequency (f clk = 80mhz, a in = -2dbfs) max19586toc04 f in (mhz) snr/sinad (db) snr sinad 70 75 85 100 80 90 105 95 110 0 406080 20 100 120 140 160 180 sfdr1/sfdr2 vs. analog input frequency (f clk = 80mhz, a in = -2dbfs) max19586toc05 f in (mhz) sfdr1/sfdr2 (dbc) sfdr2 sfdr1 -110 -105 -95 -80 -100 -90 -75 -85 -70 0 406080 20 100 120 140 160 180 hd2/hd3 vs. analog input frequency (f clk = 80mhz, a in = -2dbfs) max19586toc06 f in (mhz) hd2/hd3 (dbc) hd3 hd2 40 50 70 60 45 55 65 75 80 85 -40 -30 -25 -20 -35 -15 -10 -5 0 snr vs. analog input amplitude (f clk = 80mhz, f in = 10.10011mhz) max19586toc07 analog input amplitude (dbfs) snr (db, dbfs) snr (dbfs) snr (db) 60 80 110 90 70 100 120 -40 -30 -25 -20 -35 -15 -10 -5 0 sfdr1 vs. analog input amplitude (f clk = 80mhz, f in = 10.10011mhz) max19586toc08 analog input amplitude (dbfs) sfdr1 (dbc, dbfs) sfdr1 (dbfs) sfdr1 (dbc) sfdr = 90db reference line 60 80 110 90 70 100 120 -40 -30 -25 -20 -35 -15 -10 -5 0 sfdr2 vs. analog input amplitude (f clk = 80mhz, f in = 10.10011mhz) max19586toc09 analog input amplitude (dbfs) sfdr2 (dbc, dbfs) sfdr2 (dbfs) sfdr2 (dbc) sfdr = 90db reference line typical operating characteristics (av dd = 3.3v, dv dd = 1.8v, inp and inn driven differentially, internal reference, clkp and clkn driven differentially, c l = 5pf at digital outputs, f clk = 80mhz, t a = +25 c. unless otherwise noted, all ac data based on 32k-point fft records and under coherent sampling conditions.)
typical operating characteristics (continued) (av dd = 3.3v, dv dd = 1.8v, inp and inn driven differentially, internal reference, clkp and clkn driven differentially, c l = 5pf at digital outputs, f clk = 80mhz, t a = +25 c. unless otherwise noted, all ac data based on 32k-point fft records and under coherent sampling conditions.) 72 76 80 74 78 82 20 40 50 60 30 70 80 90 100 110 snr/sinad vs. sampling frequency (f in = 70.163683mhz, a in = -2dbfs) max19586toc16 f clk (mhz) snr/sinad (db) snr sinad 75 85 95 80 90 105 20 40 50 60 30 70 80 90 100 110 sfdr1/sfdr2 vs. sampling frequency (f in = 70.163683mhz, a in = -2dbfs) max19586toc17 f clk (mhz) sfdr/sfdr2 (dbc) 100 sfdr2 sfdr1 -110 -90 -100 -105 -95 -70 20 40 50 60 30 70 80 90 100 110 hd2/hd3 vs. sampling frequency (f in = 70.163683mhz, a in = -2dbfs) max19586toc18 f clk (mhz) hd2/hd3 (dbc) -80 -85 -75 hd3 hd2 max19586 high-dynamic-range, 16-bit, 80msps adc with -82dbfs noise floor 6 _______________________________________________________________________________________ 73 77 81 75 79 83 20 30 40 50 60 70 80 90 100 110 snr/sinad vs. sampling frequency (f in = 9.9757395mhz, a in = -2dbfs) max19586toc13 f clk (mhz) snr/sinad (db) sinad snr 75 90 110 80 100 95 115 85 105 120 sfdr/sfdr2 vs. sampling frequency (f in = 10.10011mhz, a in = -2dbfs) max19586toc14 f clk (mhz) sfdr1/sfdr2 (dbc) 20 30 40 50 60 70 80 90 100 110 sfdr1 sfdr2 -120 -90 -110 -80 -100 -70 hd2/hd3 vs. sampling frequency (f in = 10.10011mhz, a in = -2dbfs) max19586toc15 f clk (mhz) hd2/hd3 (dbc) 20 30 40 50 60 70 80 90 100 110 hd2 hd3 35 45 85 65 55 40 50 60 70 75 80 90 -40 -30 -25 -20 -35 -15 -10 -5 0 snr vs. analog input amplitude (f clk = 80mhz, f in = 70.163683mhz) max19586toc10 analog input amplitude (dbfs) snr (db, dbfs) snr (dbfs) snr (db) 40 60 100 80 50 70 90 110 -40 -30 -25 -20 -35 -15 -10 -5 0 sfdr1 vs. analog input amplitude (f clk = 80mhz, f in = 70.163683mhz) max19586toc11 analog input amplitude (dbfs) sfdr1 (dbc, dbfs) sfdr1 (dbfs) sfdr1 (dbc) sfdr = 90db reference line 40 60 100 110 80 50 70 90 120 -40 -30 -25 -20 -35 -15 -10 -5 0 sfdr2 vs. analog input amplitude (f clk = 80mhz, f in = 70.163683mhz) max19586toc12 analog input amplitude (dbfs) sfdr2 (dbc, dbfs) sfdr2 (dbfs) sfdr2 (dbc) sfdr = 90db reference line
typical operating characteristics (continued) (av dd = 3.3v, dv dd = 1.8v, inp and inn driven differentially, internal reference, clkp and clkn driven differentially, c l = 5pf at digital outputs, f clk = 80mhz, t a = +25 c. unless otherwise noted, all ac data based on 32k-point fft records and under coherent sampling conditions.) max19586 high-dynamic-range, 16-bit, 80msps adc with -82dbfs noise floor _______________________________________________________________________________________ 7 76 80 78 77 79 82 -40 -15 10 35 60 85 snr/sinad vs. temperature (f clk = 80mhz, f in = 10.10011mhz, a in = -2dbfs) max19586toc19 temperature ( c) snr/sinad (db) 81 snr sinad 80 100 90 85 95 120 -40 -15 10 35 60 85 sfdr1/sfdr2 vs. temperature (f clk = 80mhz, f in = 10.10011mhz, a in = -2dbfs) max19586toc20 temperature ( c) sfdr1/sfdr2 (dbc) 110 105 115 sfdr2 sfdr1 -115 -95 -105 -110 -100 -80 -40 -15 10 35 60 85 hd2/hd3 vs. temperature (f clk = 80mhz, f in = 10.10011mhz, a in = -2dbfs) max19586toc21 temperature ( c) hd2/hd3 (dbc) -85 -90 hd2 hd3 75 79 77 76 78 81 -40 -15 10 35 60 85 snr/sinad vs. temperature (f clk = 80mhz, f in = 70.163683mhz, a in = -2dbfs) max19586toc22 temperature ( c) snr/sinad (db) 80 snr sinad 60 100 80 70 90 120 -40 -15 10 35 60 85 sfdr1/sfdr2 vs. temperature (f clk = 80mhz, f in = 70.163683mhz, a in = -2dbfs) max19586toc23 temperature ( c) sfdr1/sfdr2 (dbc) 110 sfdr2 sfdr1 -115 -100 -80 -110 -90 -95 -75 -105 -85 -70 -40 -15 10 35 60 85 hd2/hd3 vs. temperature (f clk = 80mhz, f in = 70.163683mhz, a in = -2dbfs) max19586toc24 temperature ( c) hd2/hd3 (dbc) hd3 hd2 1000 1080 1160 1040 1120 1200 -40 -15 10 35 60 85 power dissipation vs. temperture max19586toc25 temperature ( c) power dissipation (mw) f clk = 80.00012288mhz f in = 70.163683mhz a in = -2dbfs 200 400 1200 800 600 300 500 700 900 1000 1100 1300 3.15 3.25 3.30 3.35 3.20 3.40 3.45 power dissipation vs. analog supply voltage max19586toc27 analog supply voltage (v) i avcc , p diss (ma, mw) p diss f clk = 80.00012288mhz f in = 70.163683mhz a in = -2dbfs i avcc 1.260 1.275 1.295 1.265 1.285 1.270 1.290 1.280 1.300 -40 -15 10 35 60 85 reference voltage vs. temperture max19586toc26 temperature ( c) reference voltage (v) f clk = 80.00012288mhz f in = 70.163683mhz a in = -2dbfs
typical operating characteristics (continued) (av dd = 3.3v, dv dd = 1.8v, inp and inn driven differentially, internal reference, clkp and clkn driven differentially, c l = 5pf at digital outputs, f clk = 80mhz, t a = +25 c. unless otherwise noted, all ac data based on 32k-point fft records and under coherent sampling conditions.) max19586 high-dynamic-range, 16-bit, 80msps adc with -82dbfs noise floor 8 _______________________________________________________________________________________ 1.270 1.275 1.285 1.280 1.273 1.278 1.283 1.288 1.290 3.15 3.25 3.30 3.35 3.20 3.40 3.45 reference voltage vs. analog supply voltage max19586toc28 analog supply voltage (v) reference voltage (v) f clk = 80.00012288mhz f in = 70.163683mhz a in = -2dbfs 73 75 77 74 76 81 3.15 3.25 3.30 3.35 3.20 3.40 3.45 snr/sinad vs. analog supply voltage max19586toc29 analog supply voltage (v) snr/sinad (db) 78 79 80 snr sinad f clk = 80.00012288mhz f in = 70.163683mhz a in = -2dbfs 70 80 90 75 85 110 3.15 3.25 3.30 3.35 3.20 3.40 3.45 sfdr1/sfdr2 vs. analog supply voltage max19586toc30 analog supply voltage (v) sfdr1/sfdr2 (dbc) 95 100 105 sfdr1 sfdr2 f clk = 80.00012288mhz f in = 70.163683mhz a in = -2dbfs -110 -100 -90 -105 -95 -70 3.15 3.25 3.30 3.35 3.20 3.40 3.45 hd2/hd3 vs. analog supply voltage max19586to31 analog supply voltage (v) hd2/hd3 (dbc) -85 -80 -75 hd2 hd3 f clk = 80.00012288mhz f in = 70.163683mhz a in = -2dbfs -120 -100 -80 -60 -40 -20 0 010 5 152025303540 two-tone sfdr plot (32,768-point data record) max19586 toc32 analog input frequency (mhz) amplitude (dbfs) f clk = 80mhz f in1 = 10.1001mhz f in2 = 14.871mhz a in1 = -8.04dbfs a in2 = -8.00dbfs ttsfdr = 99.6dbfs f in1 f in2 f in1 + f in2 -120 -100 -80 -60 -40 -20 0 010 5 152025303540 two-tone sfdr plot (32,768-point data record) max19586 toc33 analog input frequency (mhz) amplitude (dbfs) f clk = 80mhz f in1 = 65.1002mhz f in2 = 70.1mhz a in1 = -8.03dbfs a in2 = -8.00dbfs ttsfdr = 93.2dbfs f in2 f in1 2f in1 - f in2 0 20 70 110 50 90 10 60 100 40 30 80 120 -100 -80 -70 -60 -90 -50 -40 -30 -20 -10 0 two-tone sfdr vs. analog input amplitude (f clk = 80mhz, f in1 = 10.1mhz, f in2 = 14.87mhz) max19586toc34 analog input amplitude (dbfs) ttsfdr (dbc, dbfs) sfdr (dbfs) sfdr (dbc) sfdr = 90db reference line 0 20 70 110 50 90 10 60 100 40 30 80 120 -100 -80 -70 -60 -90 -50 -40 -30 -20 -10 0 two-tone sfdr vs. analog input amplitude (f clk = 80mhz, f in1 = 65.1mhz, f in2 = 70.1mhz) max19586toc35 analog input amplitude (dbfs) ttsfdr (dbc, dbfs) sfdr (dbfs) sfdr (dbc) sfdr = 90db reference line
max19586 high-dynamic-range, 16-bit, 80msps adc with -82dbfs noise floor _______________________________________________________________________________________ 9 pin description pin name function 1, 2, 17, 18, 19, 23, 24, 25, 55, 56 av dd analog supply voltage. provide local bypassing to ground with 0.01f and 0.1f capacitors. 3, 6 9, 12, 13, 14, 20, 21, 22, 28 agnd converter ground. analog, digital, and output-driver grounds are internally connected to the same potential. connect the converter s exposed paddle (ep) to gnd. 4 clkp differential clock, positive input terminal 5 clkn differential clock, negative input terminal 10 inp differential analog input, positive terminal 11 inn differential analog input, negative/complementary terminal 15, 16, 54 n.c. no connection. do not connect to this pin. 26 refout internal bandgap reference output 27 refin reference voltage input 29, 41, 42, 51 dv dd digital supply voltage. provide local bypassing to ground with 0.01f and 0.1f capacitors. 30, 31, 52 dgnd converter ground. digital output-driver ground. 32 d0 digital cmos output bit 0 (lsb) 33 d1 digital cmos output bit 1 34 d2 digital cmos output bit 2 35 d3 digital cmos output bit 3 36 d4 digital cmos output bit 4 37 d5 digital cmos output bit 5 38 d6 digital cmos output bit 6 39 d7 digital cmos output bit 7 40 d8 digital cmos output bit 8 43 d9 digital cmos output bit 9 44 d10 digital cmos output bit 10 45 d11 digital cmos output bit 11 46 d12 digital cmos output bit 12 47 d13 digital cmos output bit 13 48 d14 digital cmos output bit 14 49 d15 digital cmos output bit 15 (msb) 50 dav data valid output. this output can be used as a clock control line to drive an external buffer or data- acquisition system. the typical delay time between the falling edge of the converter clock and the rising edge of dav is 3.8ns. 53 dor data over-range bit. this control line flags an over-/under-range condition in the adc. if dor transitions high, an over-/under-range condition was detected. if dor remains low, the adc operates within the allowable full-scale range. ep exposed paddle. must be connected to agnd.
max19586 high-dynamic-range, 16-bit, 80msps adc with -82dbfs noise floor 10 ______________________________________________________________________________________ detailed description figure 1 provides an overview of the max19586 archi- tecture. the max19586 employs an input track-and- hold (t/h) amplifier, which has been optimized for low thermal noise and low distortion. the high-impedance differential inputs to the t/h amplifier (inp and inn) are self-biased at 2.2v, and support a full-scale 2.56v p-p differential input voltage. the output of the t/h amplifier is applied to a multistage pipelined adc core, which is designed to achieve a very low thermal noise floor and low distortion. a clock buffer receives a differential input clock wave- form and generates a low-jitter clock signal for the input t/h. the signal at the analog inputs is sampled at the rising edge of the differential clock waveform. the dif- ferential clock inputs (clkp and clkn) are high- impedance inputs, are self-biased at 1.6v, and support differential clock waveforms from 1v p-p to 5v p-p . the outputs from the multistage pipelined adc core are delivered to error correction and formatting logic, which deliver the 16-bit output code in two s-comple- ment format to digital output drivers. the output drivers provide 1.8v cmos-compatible outputs. analog inputs (inp, inn) the signal inputs to the max19586 (inp and inn) are balanced differential inputs. this differential configura- tion provides immunity to common-mode noise coupling and rejection of even-order harmonic terms. the differ- ential signal inputs to the max19586 should be ac-cou- pled and carefully balanced to achieve the best dynam- ic performance (see differential, ac-coupled analog inputs in the applications information section for more details). ac-coupling of the input signal is required because the max19586 inputs are self-biasing as shown in figure 2. although the track-and-hold inputs are high impedance, the actual differential input imped- ance is nominally 10k ? because of the two 5k ? resis- tors connected to the common-mode bias circuitry. avoid injecting any dc leakage currents into these ana- log inputs. exceeding a dc leakage current of 10a shifts the self-biased common-mode level, adversely affecting the converter s performance. on-chip reference circuit the max19586 incorporates an on-chip 1.28v, low-drift bandgap reference. this reference potential establish- es the full-scale range for the converter, which is nomi- nally 2.56v p-p differential (figure 3). the internal reference voltage can be monitored by refout. to use the internal reference voltage the reference input (refin) must be connected to refout through a 10k ? resistor. bypass both pins with sepa- rate 1f capacitors to agnd. the max19586 also allows an external reference source to be connected to refin, enabling the user to overdrive the internal bandgap reference. refin accepts a 1.28v 10% input voltage range. max19586 clock buffer cmos output drivers cmos driver av dd agnd dav dv dd clkp clkn inp inn refout refin reference pipeline adc dor d0?15 dgnd t/h figure 1. block diagram
max19586 high-dynamic-range, 16-bit, 80msps adc with -82dbfs noise floor ______________________________________________________________________________________ 11 clock inputs (clkp, clkn) the differential clock buffer for the max19586 has been designed to accept an ac-coupled clock waveform. like the signal inputs, the clock inputs are self-biasing. in this case, the self-biased potential is 1.6v and each input is connected to the reference potential with a 5k ? resistor. consequently, the differential input resistance associated with the clock inputs is 10k ? . while differ- ential clock signals as low as 0.5v p-p can be used to drive the clock inputs, best dynamic performance is achieved with 1v p-p to 5v p-p clock input voltage levels. jitter on the clock signal translates directly to jitter (noise) on the sampled signal. therefore, the clock source must be a very low-jitter (low-phase-noise) source. additionally, extremely low phase-noise oscilla- tors and bandpass filters should be used to obtain the true ac performance of this converter. see the differential, ac-coupled clock inputs and testing the max19586 topics in the applications information sec- tion for additional details on the subject of driving the clock inputs. system timing requirements figure 4 depicts the general timing relationships for the signal input, clock input, data output, and dav output. figure 5 shows the detailed timing specifications and signal relationships, as defined in the electrical characteristics table. the max19586 samples the input signal on the rising edge of the input clock. output data is valid on the ris- ing edge of the dav signal, with a 7 clock-cycle data latency. note that the clock duty cycle should typically be 50% 10% for proper operation. digital outputs (d0?15, dav, dor) although designed for low-voltage 1.8v logic systems, the logic-high level of the low-voltage cmos-compati- ble digital outputs (d0 d15, dav, and dor) offer some flexibility, as it allows the user to select the digital volt- age within the 1.7v to 1.9v range. for best performance, the capacitive loading on the digital outputs of the max19586 should be kept as low as possible (< 10pf). due to the current-limited data- output driver of the max19586, large capacitive loads increase the rise and fall time of the data and can make it more difficult to register the data into the next ic. the loading capacitance can be kept low by keeping the output traces short and by driving a single cmos buffer or latch input (as opposed to multiple cmos inputs). the output data is in two s-complement format, as illustrated in table 1. data is valid at the rising edge of dav (figures 4, 5). dav may be used as a clock signal to latch the output data. note that the dav output driver is not current lim- ited, hence it allows for higher capacitive loading. t/h amplifier t/h amplifier to first quantizer stage to first quantizer stage inp inn 5k ? 5k ? ota figure 2. simplified analog input architecture -640mv +640mv inp inn 2.56v p-p differential fsr common-mode voltage (2.2v) figure 3. full-scale voltage range
max19586 high-dynamic-range, 16-bit, 80msps adc with -82dbfs noise floor 12 ______________________________________________________________________________________ figure 4. general system and output timing diagram 7 clock-cycle latency n n + 1 n - 7 n - 6 n - 5 n - 4 n - 3 n - 2 n - 1 n n + 2 n + 3 n + 4 n + 6 n + 7 n + 5 analog input clock input d0 d15 dav figure 5. detailed timing information for clock operation clkn clkp d0 d15 dor dav t dat inp inn n - 4 t dav t s t h t dnv t dgv t a t clkp t clkn n - 7 n n + 1 n + 2 n + 3 n - 6 n - 5 encode at clkp - clkn > 0 (rising edge) t clkp clkp - clkn > 0 t clkn clkp - clkn < 0 t ad effective aperture delay t dat delay from clkp to output data transition t dav delay from clkn to data valid clock dav t dnv clkp rising edge to data not valid t dgv clkp rising edge to data guaranteed valid t s data setup time before rising dav t h data hold time after rising dav
max19586 high-dynamic-range, 16-bit, 80msps adc with -82dbfs noise floor ______________________________________________________________________________________ 13 the converter s dor output signal is used to identify over- and under-range conditions. if the input signal exceeds the positive or negative full-scale range for the max19586 then dor will be asserted high. the timing for dor is identical to the timing for the data outputs, and dor therefore provides an over-range indication on a sample-by-sample basis. applications information differential, ac-coupled clock inputs the clock inputs to the max19586 are driven with an ac-coupled differential signal, and best performance is achieved under these conditions. however, it is often the case that the available clock source is single-ended. figure 6 demonstrates one method for converting a sin- gle-ended clock signal into a differential signal with a transformer. in this example, the transformer turns ratio from the primary to secondary side is 1:1.414. the impedance ratio from primary to secondary is the square of the turns ratio, or 1:2. so terminating the sec- ondary side with a 100 ? differential resistance results in a 50 ? load looking into the primary side of the trans- former. the termination resistor in this example is com- prised of the series combination of two 50 ? resistors with their common node ac-coupled to ground. figure 6 illustrates the secondary side of the trans- former to be coupled directly to the clock inputs. since the clock inputs are self-biasing, the center tap of the transformer must be ac-coupled to ground or left float- ing. if the center tap of the transformer s secondary side is dc-coupled to ground, it is necessary to add blocking capacitors in series with the clock inputs. clock jitter is generally improved if the clock signal has a high slew rate at the time of its zero-crossing. therefore, if a sinusoidal source is used to drive the clock inputs the clock amplitude should be as large as possible to maximize the zero-crossing slew rate. the back-to-back schottky diodes shown in figure 6 are not required as long as the input signal is held to a differen- tial voltage potential of 3v p-p or less. if a larger ampli- tude signal is provided (to maximize the zero-crossing slew rate), then the diodes serve to limit the differential signal swing at the clock inputs. note that all ac speci- fications for the max19586 are measured within this configuration and with an input clock amplitude of approximately 12dbm. any differential mode noise coupled to the clock inputs translates to clock jitter and degrades the snr perfor- mance of the max19586. any differential mode coupling of the analog input signal into the clock inputs results in harmonic distortion. consequently, it is important that the clock lines be well isolated from the analog signal input and from the digital outputs. see the signal routing sec- tion for more discussion on the subject of noise coupling. differential, ac-coupled analog inputs the analog inputs inp and inn are driven with a differ- ential ac-coupled signal. it is important that these inputs be accurately balanced. any common-mode sig- nal applied to these inputs degrades even-order distor- tion terms. therefore, any attempt at driving these inputs in a single-ended fashion will result in significant even-order distortion terms. figure 7 presents one method for converting a single- ended signal to a balanced differential signal using a transformer. the primary-to-secondary turns ratio in this example is 1:1.414. the impedance ratio is the square of the turns ratio, so in this example the impedance ratio is 1:2. to achieve a 50 ? input impedance at the primary side of the transformer, the secondary side is terminated with a 100 ? differential load. this load, in shunt with the differential input resistance of the max19586, results in a 100 ? differential load on the secondary side. it is rea- table 1. max19586 digital output coding inp analog voltage level inn analog voltage level d15 d0 two s-complement code v cm + 0.64v v cm - 0.64v 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (positive full-scale) v cm v cm 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (midscale + ) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (midscale - ) v cm - 0.64v v cm + 0.64v 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (negative full-scale)
max19586 high-dynamic-range, 16-bit, 80msps adc with -82dbfs noise floor 14 ______________________________________________________________________________________ sonable to use a larger transformer turns ratio to achieve a larger signal step-up, and this may be desirable to relax the drive requirements for the circuitry driving the max19586. however, the larger the turns ratio, the larg- er the effect of the differential input impedance of the max19586 on the primary-referred input impedance. as stated previously, the signal inputs to the max19586 must be accurately balanced to achieve the best even- order distortion performance. figure 6. transformer-coupled clock input configuration agnd clkp clkn dgnd d0 d15 av dd dv dd 16 max19586 0.1 f inp inn t2-1t-kk81 49.9 ? 49.9 ? 0.1 f back-to-back diode figure 7. transformer-coupled analog input configuration with primary-side balun transformer agnd clkp clkn dgnd d0 d15 av dd dv dd 16 max19586 0.1 f inp inn adt2-1t t1-1t-kk81 49.9 ? 49.9 ? positive terminal 0.1 f
max19586 high-dynamic-range, 16-bit, 80msps adc with -82dbfs noise floor ______________________________________________________________________________________ 15 one note of caution in relation to transformers is impor- tant. any dc current passed through the primary or secondary windings of a transformer may magnetically bias the transformer core. when this happens the trans- former is no longer accurately balanced and a degra- dation in the distortion of the max19586 may be observed. the core must be demagnetized to return to balanced operation. testing the max19586 the max19586 has a very low thermal noise floor (-82dbfs) and very low jitter (< 100fs). as a conse- quence, test system limitations can easily obscure the performance of the adc. figure 8a is a block diagram of a conventional high-speed adc test system. the input signal and the clock source are generated by low- phase-noise synthesizers (e.g., agilent 8644b). bandpass filters in both the signal and the clock paths then attenuate noise and harmonic components. figure 8b shows the resulting power spectrum, which results from this setup for a 70mhz input tone and an 80msps clock. note the substantial lift in the noise floor near the carrier. the bandwidth of this particular noise- floor lift near the carrier corresponds to the bandwidth of the filter in the input signal path. figure 8c illustrates the impact on the spectrum if the input frequency is shifted away from the center fre- quency of the input signal filter. note that the funda- mental tone has moved, but the noise-floor lift remains in the same location. this is evidence of the validity of the claim that the lift in the noise floor is due to the test system and not the adc. in this figure, the magnitude of the lift in the noise floor increased relative to the pre- vious figure because the signal is located on the skirt of the filter and the signal amplitude had to be increased to obtain a signal near full scale. to truly reveal the performance of the max19586, the test system performance must be improved substantially. figure 8d depicts such an improved test system. in this system, the synthesizers provide reference inputs to two dedicated low-noise phase-locked loops (plls), one cen- tered at approximately 80mhz (for the clock path) and the other centered at 70mhz (for the signal path). the oscilla- tors in these plls are very low-noise oscillators, and the figure 8a. standard high-speed adc test setup (simplified block diagram) 10db signal path clock path bandpass filter bandpass filter agilent 8644b agilent 8644b 3db pad both signal generators are phase-locked max19586 figure 8b. 70mhz fft with standard high-speed adc test setup -120 -100 -80 -60 -40 -20 0 010 5 152025303540 fft plot (32,768-point data record) analog input frequency (mhz) power (dbfs) 2 3 f clk = 80.00012288mhz f in = 70.163683mhz a in = -2dbfs figure 8c. 68mhz fft with standard high-speed adc test setup -120 -100 -80 -60 -40 -20 0 010 5 152025303540 fft plot (32,768-point data record) frequency (mhz) power (dbfs) 2 3 f clk = 80.00012288mhz f in = 68mhz a in = -2dbfs carrier was intentionally lowered by 2mhz to show the stationary behavior of the noise
max19586 high-dynamic-range, 16-bit, 80msps adc with -82dbfs noise floor 16 ______________________________________________________________________________________ plls act as extremely narrow bandwidth filters (on the order of 20hz) to attenuate the noise of the synthesizers. the system provides a total system jitter on the order of 20fs. note that while the low-noise oscillators could be used by themselves without being locked to their respec- tive signal sources, this would result in ffts that are not coherent and which would require windowing. figure 8e is an fft plot of the spectrum obtained when the improved test system is employed. the noise-floor lift in the vicinity of the carrier is now almost completely eliminated. the snr associated with this fft is about 79.1db, whereas the snr obtained using the standard test system is on the order of 77.6db. figure 8d. improved test system employing narrowband plls (simplified block diagram) ref signal pll vcxo 10db variable attenuator signal path clock path bandpass filter bandpass filter tune low-noise pll agilent 8644b ref signal pll vcxo 10db tune low-noise pll agilent 8644b 3db pad both signal generators are phase-locked max19586 figure 8e. 70mhz fft with improved high-speed adc test setup -120 -100 -80 -60 -40 -20 0 010 5 152025303540 fft plot (32,768-point data record) analog input frequency (mhz) analog power (dbfs) 2 3 f clk = 80.00012288mhz f in = 70.163683mhz a in = -2dbfs figure 8f. snr vs. system jitter performance graph 110 60 10 100 1000 snr vs. rms jitter performance 65 rms jitter (fs) snr (db) 80 95 70 85 100 75 90 105 input frequency = 140mhz input frequency = 70mhz
max19586 high-dynamic-range, 16-bit, 80msps adc with -82dbfs noise floor ______________________________________________________________________________________ 17 figure 8f demonstrates the impact of test system jitter on measured snr. the figure plots snr due to test system jitter only, neglecting all other sources of noise, for two different input frequencies. for example, note that for a 70mhz input frequency a test system jitter number of 100fs results in an snr (due to the test sys- tem alone) of about 87.1db. in the case of the max19586, which has a -82dbfs noise floor, this is not an inconsequential amount of additional noise. in conclusion, careful attention must be paid to both the input signal source and the clock signal source, if the true performance of the max19586 is to be properly characterized. dedicated plls with low-noise vcos, such as those used in figure 8d, are capable of provid- ing signals with the required low jitter performance. layer assignments the max19586 ev kit is a 6-layer board, and the assignment of layers is discussed in this context. it is recommended that the ground plane be on a layer between the signal routing layer and the supply routing layer(s). this prevents coupling from the supply lines into the signal lines. the max19586 ev kit pc board places the signal lines on the top (component) layer and the ground plane on layer 2. any region on the top layer not devoted to signal routing is filled with the ground plane with vias to layer 2. layers 3 and 4 are devoted to supply routing, layer 5 is another ground plane, and layer 6 is used for the placement of addi- tional components and for additional signal routing. a four-layer implementation is also feasible using layer 1 for signal lines, layer 2 as a ground plane, layer 3 for supply routing, and layer 4 for additional signal routing. however, care must be taken to ensure that the clock and signal lines are isolated from each other and from the supply lines. signal routing to preserve good even-order distortion, the signal lines (those traces feeding the inp and inn inputs) must be carefully balanced. to accomplish this, the signal traces should be made as symmetric as possible, meaning that each of the two signal traces should be the same length and should see the same parasitic environment. as mentioned previously, the signal lines must be isolated from the supply lines to prevent cou- pling from the supplies to the inputs. this is accom- plished by making the necessary layer assignments as described in the previous section. additionally, it is cru- cial that the clock lines be isolated from the signal lines. on the max19586 ev kit this is done by routing the clock lines on the bottom layer (layer 6). the clock lines then connect to the adc through vias placed in close proximity to the device. the clock lines are isolated from the supply lines as well by virtue of the ground plane on layer 5. as with all high-speed designs, digital output traces should be kept as short as possible to minimize capaci- tive loading. the ground plane on layer 2 beneath these traces should not be removed so that the digital ground return currents have an uninterrupted path back to the bypass capacitors. grounding the practice of providing a split ground plane in an attempt to confine digital ground-return currents has often been recommended in adc application literature. however, for converters such as the max19586 it is strongly recommended to employ a single, uninterrupt- ed ground plane. the max19586 ev kit achieves excel- lent dynamic performance with such a ground plane. the exposed paddle of the max19586 should be sol- dered directly to a ground pad on layer 1 with vias to the ground plane on layer 2. this provides excellent electrical and thermal connections to the pc board. supply bypassing the max19586 ev kit uses 220f capacitors (and smaller values such as 47f and 2f) on power-supply lines av dd and dv dd to provide low-frequency bypassing. the loss (series resistance) associated with these capacitors is beneficial in eliminating high-q sup- ply resonances. ferrite beads are also used on each of the power-supply lines to enhance supply bypassing (figure 9). combinations of small value (0.01f and 0.1f), low- inductance surface-mount capacitors should be placed at each supply pin or each grouping of supply pins to attenuate high-frequency supply noise. place these capacitors on the top side of the board and as close to the converter as possible with short connections to the ground plane. parameter definitions offset error offset error is a figure of merit that indicates how well the actual transfer function matches the ideal transfer function at a single point. ideally, the midscale max19586 transition occurs at 0.5 lsb above mid- scale. the offset error is the amount of deviation between the measured midscale transition point and the ideal midscale transition point.
max19586 high-dynamic-range, 16-bit, 80msps adc with -82dbfs noise floor 18 ______________________________________________________________________________________ gain error gain error is a figure of merit that indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. the slope of the actual transfer function is measured between two data points: positive full scale and negative full scale. ideally, the positive full-scale max19586 transition occurs at 1.5 lsbs below positive full scale, and the negative full- scale transition occurs at 0.5 lsb above negative full scale. the gain error is the difference of the measured transition points minus the difference of the ideal transi- tion points. small-signal noise floor (ssnf) small-signal noise floor is the integrated noise and dis- tortion power in the nyquist band for small-signal inputs. the dc offset is excluded from this noise calcu- lation. for this converter, a small signal is defined as a single tone with an amplitude of less than -35dbfs. this parameter captures the thermal and quantization noise characteristics of the data converter and can be used to help calculate the overall noise figure of a digi- tal receiver signal path. signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantiza- tion error only and results directly from the adc s reso- lution (n bits): snr[max] = 6.02 x n + 1.76 in reality, there are other noise sources besides quanti- zation noise: thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the rms signal to the rms noise. rms noise includes all spec- tral components to the nyquist frequency excluding the fundamental, the first four harmonics (hd2 through hd5), and the dc offset. snr = 20 x log (signal rms / noise rms ) signal-to-noise plus distortion (sinad) sinad is computed by taking the ratio of the rms sig- nal to the rms noise plus distortion. rms noise plus distortion includes all spectral components to the nyquist frequency excluding the fundamental and the dc offset. figure 9. grounding, bypassing, and decoupling recommendations for the max19586 agnd bypassing?dc level bypassing?oard level analog power- supply source dgnd agnd dgnd d0 d15 47 f 2 f 0.1 f 0.1 f 220 f av dd dv dd 16 max19586 0.01 f 0.01 f av dd ferrite bead digital power- supply source 47 f 2 f 220 f dv dd ferrite bead
max19586 high-dynamic-range, 16-bit, 80msps adc with -82dbfs noise floor ______________________________________________________________________________________ 19 spurious-free dynamic range (sfdr1 and sfdr2) sfdr is the ratio expressed in decibels of the rms amplitude of the fundamental (maximum signal compo- nent) to the rms value of the next largest spurious component, excluding dc offset. sfdr1 reflects the max19586 spurious performance based on worst 2nd- or 3rd-order harmonic distortion. sfdr2 is defined by the worst spurious component excluding 2nd- and 3rd- order harmonic spurs and dc offset. two-tone spurious-free dynamic range (ttsfdr) two-tone sfdr is the ratio of the full scale of the con- verter to the rms value of the peak spurious compo- nent. the peak spurious component can be related to the intermodulation distortion components, but does not have to be. two-tone sfdr for the max19586 is expressed in dbfs. two-tone intermodulation distortion (ttimd) imd is the total power of the im2 to im5 intermodulation products to the nyquist frequency relative to the total input power of the two input tones f in1 and f in2 . the individual input tone levels are at -8dbfs. the inter- modulation products are as follows: second-order intermodulation products (im2): f in1 + f in2 , f in2 - f in1 third-order intermodulation products (im3): 2 x f in1 - f in2 , 2 x f in2 - f in1 , 2 x f in1 + f in2 , 2 x f in2 + f in1 fourth-order intermodulation products (im4): 3 x f in1 - f in2 , 3 x f in2 - f in1 , 3 x f in1 + f in2 , 3 x f in2 + f in1 , 2 x f in1 - 2 x f in2 fifth-order intermodulation products (im5): 3 x f in1 - 2 x f in2 , 3 x f in2 - 2 x f in1 , 3 x f in1 + 2 x f in2 , 3 x f in2 + 2 x f in1 , 4 x f in1 - f in2 note that the two-tone intermodulation distortion is mea- sured with respect to a single-carrier amplitude and not the peak-to-average input power of both input tones. aperture jitter aperture jitter (t aj ) represents the sample-to-sample variation in the aperture delay specification. aperture delay aperture delay (t ad ) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (figure 5).
max19586 high-dynamic-range, 16-bit, 80msps adc with -82dbfs noise floor maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products. inc. maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products. inc. maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products. inc. maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) freed 56l thin qfn.eps
e nglish ? ???? ? ??? ? ??? what's ne w p roducts solutions de sign ap p note s sup p ort buy comp any me mbe rs max19586 part number table notes: see the max19586 quickview data sheet for further information on this product family or download the max19586 full data sheet (pdf, 388kb). 1. other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 2. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 3. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming c onventions . 4. * some packages have variations, listed on the drawing. "pkgc ode/variation" tells which variation the product uses. 5. part number free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis MAX19586ETN-TD -40c to +85c rohs/lead-free: no max19586etn+td -40c to +85c rohs/lead-free: yes max19586etn-d thin qfn;56 pin;8x8x0.8mm dwg: 21-0135e (pdf) use pkgcode/variation: t5688-2 * -40c to +85c rohs/lead-free: no materials analysis max19586etn+d thin qfn;56 pin;8x8x0.8mm dwg: 21-0135e (pdf) use pkgcode/variation: t5688+2 * -40c to +85c rohs/lead-free: yes materials analysis didn't find what you need? c ontac t us: send us an email c opyright 2 0 0 7 by m axim i ntegrated p roduc ts , dallas semic onduc tor ? legal n otic es ? p rivac y p olic y

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